ERROVR=ERROVR_0, BIT1ERR=BIT1ERR_0, TWRNINT=TWRNINT_0, BIT1ERR_FAST=BIT1ERR_FAST_0, BOFFINT=BOFFINT_0, RXWRN=RXWRN_0, SYNCH=SYNCH_0, WAKINT=WAKINT_0, BOFFDONEINT=BOFFDONEINT_0, CRCERR_FAST=CRCERR_FAST_0, TXWRN=TXWRN_0, ERRINT_FAST=ERRINT_FAST_0, TX=TX_0, STFERR_FAST=STFERR_FAST_0, CRCERR=CRCERR_0, FRMERR_FAST=FRMERR_FAST_0, IDLE=IDLE_0, STFERR=STFERR_0, FRMERR=FRMERR_0, ACKERR=ACKERR_0, FLTCONF=FLTCONF_0, BIT0ERR_FAST=BIT0ERR_FAST_0, BIT0ERR=BIT0ERR_0, RX=RX_0, RWRNINT=RWRNINT_0, ERRINT=ERRINT_0
Error and Status 1 register
| WAKINT | Wake-Up Interrupt 0 (WAKINT_0): No such occurrence. 1 (WAKINT_1): Indicates a recessive to dominant transition was received on the CAN bus. |
| ERRINT | Error Interrupt 0 (ERRINT_0): No such occurrence. 1 (ERRINT_1): Indicates setting of any Error Bit in the Error and Status Register. |
| BOFFINT | Bus Off Interrupt 0 (BOFFINT_0): No such occurrence. 1 (BOFFINT_1): FlexCAN module entered Bus Off state. |
| RX | FlexCAN In Reception 0 (RX_0): FlexCAN is not receiving a message. 1 (RX_1): FlexCAN is receiving a message. |
| FLTCONF | Fault Confinement State 0 (FLTCONF_0): Error Active 1 (FLTCONF_1): Error Passive 2 (FLTCONF_2): Bus Off |
| TX | FlexCAN In Transmission 0 (TX_0): FlexCAN is not transmitting a message. 1 (TX_1): FlexCAN is transmitting a message. |
| IDLE | IDLE 0 (IDLE_0): No such occurrence. 1 (IDLE_1): CAN bus is now IDLE. |
| RXWRN | Rx Error Warning 0 (RXWRN_0): No such occurrence. 1 (RXWRN_1): RXERRCNT is greater than or equal to 96. |
| TXWRN | TX Error Warning 0 (TXWRN_0): No such occurrence. 1 (TXWRN_1): TXERRCNT is greater than or equal to 96. |
| STFERR | Stuffing Error 0 (STFERR_0): No such occurrence. 1 (STFERR_1): A Stuffing Error occurred since last read of this register. |
| FRMERR | Form Error 0 (FRMERR_0): No such occurrence. 1 (FRMERR_1): A Form Error occurred since last read of this register. |
| CRCERR | Cyclic Redundancy Check Error 0 (CRCERR_0): No such occurrence. 1 (CRCERR_1): A CRC error occurred since last read of this register. |
| ACKERR | Acknowledge Error 0 (ACKERR_0): No such occurrence. 1 (ACKERR_1): An ACK error occurred since last read of this register. |
| BIT0ERR | Bit0 Error 0 (BIT0ERR_0): No such occurrence. 1 (BIT0ERR_1): At least one bit sent as dominant is received as recessive. |
| BIT1ERR | Bit1 Error 0 (BIT1ERR_0): No such occurrence. 1 (BIT1ERR_1): At least one bit sent as recessive is received as dominant. |
| RWRNINT | Rx Warning Interrupt Flag 0 (RWRNINT_0): No such occurrence. 1 (RWRNINT_1): The Rx error counter transitioned from less than 96 to greater than or equal to 96. |
| TWRNINT | Tx Warning Interrupt Flag 0 (TWRNINT_0): No such occurrence. 1 (TWRNINT_1): The Tx error counter transitioned from less than 96 to greater than or equal to 96. |
| SYNCH | CAN Synchronization Status 0 (SYNCH_0): FlexCAN is not synchronized to the CAN bus. 1 (SYNCH_1): FlexCAN is synchronized to the CAN bus. |
| BOFFDONEINT | Bus Off Done Interrupt 0 (BOFFDONEINT_0): No such occurrence. 1 (BOFFDONEINT_1): FlexCAN module has completed Bus Off process. |
| ERRINT_FAST | Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set 0 (ERRINT_FAST_0): No such occurrence. 1 (ERRINT_FAST_1): Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. |
| ERROVR | Error Overrun bit 0 (ERROVR_0): Overrun has not occurred. 1 (ERROVR_1): Overrun has occurred. |
| STFERR_FAST | Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 0 (STFERR_FAST_0): No such occurrence. 1 (STFERR_FAST_1): A Stuffing Error occurred since last read of this register. |
| FRMERR_FAST | Form Error in the Data Phase of CAN FD frames with the BRS bit set 0 (FRMERR_FAST_0): No such occurrence. 1 (FRMERR_FAST_1): A Form Error occurred since last read of this register. |
| CRCERR_FAST | Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 0 (CRCERR_FAST_0): No such occurrence. 1 (CRCERR_FAST_1): A CRC error occurred since last read of this register. |
| BIT0ERR_FAST | Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 0 (BIT0ERR_FAST_0): No such occurrence. 1 (BIT0ERR_FAST_1): At least one bit sent as dominant is received as recessive. |
| BIT1ERR_FAST | Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 0 (BIT1ERR_FAST_0): No such occurrence. 1 (BIT1ERR_FAST_1): At least one bit sent as recessive is received as dominant. |